1. Field of the Invention
The invention relates to a link bus between control chipsets and an arbitration method thereof. More particularly, the invention provides a bus structure that is capable of dynamically adjusting the transmission direction of AD buses and an arbitration method thereof. The bus structure of the invention comprises a first AD bus and a second AD bus placed between a first control chip and a second control chip. Each control chip respectively has a high access priority in respect of one AD bus. According to the load of each AD bus, each control chip can dynamically drive to control the other AD bus, thereby improving the transmission efficiency between the control chips.
2. Description of the Related Art
The system architecture of conventional computers is principally constituted of the peripheral component interface (PCI) system, in which the central processor unit (CPU) connects through a host bridge (for example, north bridge chip) to the PCI bus. In turn, the PCI bus respectively connects to the masters of various PCI-compatible peripheral devices, such as a graphic adapter, an expansion bus bridge, a LAN adapter, or a SCSI host bus adapter, etc.
As developments are made in the information technology and semiconductor manufacture, the control chip (for example, south bridge chip) progressively integrates more peripheral device masters. Because the peripheral devices controlled by the south bridge chip become numerous, the data transmission with the north bridge chip or the CPU consequently also increases. In the traditional PCI system architecture, the south bridge chip must commonly share the bandwidth of the PCI bus, which usually causes delay of data transmission and undesirably affects the general performance of the system.
The prior art has partly solved the above problem, as disclosed in the Taiwanese Patent No. 468112, entitled “Arbitration method for link bus between control chipsets”, and incorporated herein by reference. FIG. 1 is a schematic view illustrating the solution proposed by the aforementioned reference. A CPU 14 connects through a north bridge chip 10 to a memory 16, an AGP bus and a south bridge chip 12. The south bridge chip 12 respectively connects through a PCI bus and an ISA bus to various peripheral devices.
A link bus between control chipsets 18 is placed between the north bridge chip 10 and the south bridge chip 12. The bus 18 principally comprises: an address/data (AD) bus 186 with a set of eight bi-directional signal lines, a bi-directional bit enable signal line 185, an up link command signal line 187 and an up link strobe signal line 189 respectively driven by the south bridge chip 12, and a down link command signal line 181 and a down link strobe signal line 183 respectively driven by the north bridge chip 10.
Because the AD bus 186 is a bi-directional common bus, an arbitration mechanism is usually needed between the north bridge chip 10 and the south bridge chip 12 to achieve an effective utilization of the AD bus without conflict. In the Taiwanese Patent No. 46812, one control chip, for example the north bridge chip, usually possesses the control of the bus, while the other control chip, for example the south bridge chip, has a higher priority on the bus. When the south bridge chip transmits a bus request signal, the north bridge chip must immediately, or after the bus command currently executed is completed, switch the control of the bus to the south bridge chip. Through this known arbitration method, the link bus between control chipsets can be effectively used, and the data transmission is independently performed without commonly sharing the bandwidth of the PCI bus with other peripheral devices.
However the above technical solution of the prior art may increase the general transmission efficiency, there may be something for further improvements. For example, because one single bi-directional common AD bus is implemented, the time of bus utilization may be inadequately allocated when there is a simultaneous need from both north bridge chip and south bridge chip. Moreover, a turn-around cycle of the clock cycle is usually necessary to hand over the bus utilization. To prevent the south bridge chip from erroneously assuming that the north bridge chip is not controlling the bus while the north bridge chip has already transmitted a command and is in standby for executing the next data transmission, waiting a predetermined cycle further is necessary after the south bridge chip has transmitted the bus request signal to access the bus. This turn-around and wait create a time interval during which no data transmission is performed, which constitutes an inefficiency use of time.